This invention arose from challenges associated with fabrication of SRAM circuitry where there is a desirability of fabricating different field effect transistors with different gate dielectric layer thicknesses. The invention will have applicability to other circuitry, such as dynamic random access memory (DRAM) and logic circuitry, as the artisan will appreciate, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine Of Equivalents.
An SRAM cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. The different output voltages correspond to a binary stored "1" or a "0". Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable voltage differential between the two nodes of the cell. The polarity of this voltage difference is sensed by external circuitry to determine the operating state of the memory cell. The two possible output voltages produced by a static memory cell are determined by the upper and lower circuit supply voltages. Intermediate output voltages and the performance of the devices in the SRAM cell itself.
The operation of a static memory cell is in contrast to other types of memory cells, such as DRAM cells, which do not have stable operating states. A DRAM cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than very short time periods.
FIG. 1 shows an example prior art SRAM cell 350 such as is typically used in high-density static random access memories. Static memory cell 350 comprises n-channel pull down (driver) transistors 380 and 382 having drains respectively connected to load resistors 384 and 386. Transistors 380 and 382 are typically metal oxide silicon field effect transistors (MOSFETs) formed in an underlying silicon semiconductor substrate.
The source regions of transistors 380 and 382 are tied to a low reference or circuit supply voltage, labelled V.sub.SS which is typically referred to as "ground." Resistors 384 and 386 are respectively connected in series between a high reference or circuit supply voltage, labelled V.sub.CC, and the drains of the corresponding transistors 380 and 382. The drain of transistor 382 is connected to the gate of transistor 380 by a line 376, and the drain of transistor 380 is connected to the gate of transistor 382 by a line 374 to form flip-flop having a pair of complementary two-state outputs.
A memory flip-flop, such as that described above in connection with FIG. 1, forms one memory element of an integrated array of static memory elements. A pair of access transistors, such as access transistors 390 and 392, are provided to selectively address and access individual memory elements within the array. Access transistor 390 has one active terminal connected to the drain of transistor 380. Access transistor 392 has one active terminal connected to the drain of transistor 382. A plurality of complementary column line pairs, such as the single pair of complementary column lines 352 and 354 as shown, are connected to the remaining active terminals of access transistors 390 and 392, respectively. A row line 356 is connected to the gates of access transistors 390 and 392.
Reading static memory cell 350 requires activating row line 356 to connect outputs 368 and 372 to column lines 352 and 354. Writing to static memory cell 350 requires first placing selected complementary logic voltages on column lines 352 and 354, and then activating row line 356 to connect those logic voltages to outputs 368 and 372. This forces the outputs to the selected logic voltages, which will be maintained as long as power is supplied to the memory cell, or until the memory cell is reprogrammed.
Transistors 380, 382, 390 and 392 are typically fabricated to be NMOS field effect transistors formed from common conductive gate and gate dielectric layers. Typical SRAM circuitry fabrication also includes fabricating other circuitry external to the memory cell and array, some of which utilizes PMOS transistors. In some instances, it would be desirable to provide some of the PMOS transistors with different thickness gate dielectric layers than that used for the NMOS SRAM cell transistors.